EPF10K100AFC484-2

Product Summary

The EPF10K100AFC484-2 is an Embedded Programmable Logic Device. Based on reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates all features necessary to implement common gate array megafunctions. With up to 250,000 gates, the EPF10K100AFC484-2 provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. The EPF10K100AFC484-2 is reconfigurable, which allows 100% testing prior to shipment.

Parametrics

EPF10K100AFC484-2 absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –2.0 to 7.0 V; (2)VI, DC input voltage: –2.0 to 7.0 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature No bias: –65 to 150 ℃; (5)TAMB, Ambient temperature Under bias –65 to 135 ℃; (6)TJ, Junction temperature: at Ceramic packages, under bias: 150 ℃; at PQFP, TQFP, RQFP, and BGA packages, under bias: 135 ℃.

Features

EPF10K100AFC484-2 features: (1)Embedded array for implementing megafunctions, such as efficient memory and specialized logic functions; (2)Logic array for general logic functions; (3)10,000 to 250,000 typical gates; (4)Up to 40,960 RAM bits; 2,048 bits per embedded array block(EAB), all of which can be used without reducing logic capacity; (5)MultiVoltTM I/O interface support; (6)5.0-V tolerant input pins in FLEX 10KA devices; (7)Low power consumption (typical specification less than 0.5 mA in standby mode for most devices); (8)FLEX 10K and FLEX 10KA devices support peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2; (9)FLEX 10KA devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3-V PCI compliance; (10)Select FLEX 10KA devices support 5.0-V PCI buses with eight or fewer loads; (11)Built-in Joint Test Action Group (JTAG) boundary-scan test(BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming any device logic.

Diagrams